Voltage level translator circuits are useful in certain applications, including wireless handsets, notebook computers and personal digital assistants (PDAs) and, more particularly in SRAM cells, which run on two or more different voltage levels. For example, circuitry utilized with such portable applications may be configured so that a portion of the circuitry, such as, for example, input/output (IO) buffers, runs at a higher voltage level, while another portion of the circuitry, e.g., core logic, runs at a lower voltage level. This difference in voltage levels often necessitates the use of a voltage level translator circuit for interfacing between the multiple voltage levels.
Conventional voltage level translator circuits have been found to be unreliable at certain process, voltage and/or temperature (PVT) conditions. In fact, it has been found that conventional level translators and latch circuitry is slow as logic depth is high. Also, the conventional level translator and latch circuitry has high setup time. Moreover, the clock and wordline propagation delay in such conventional configurations can be high. In addition, conventional latches are not well suited for fenced architectures.